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Commit 32a70344 authored by Hasak's avatar Hasak
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.gitignore 0 → 100644
View file @ 32a70344
# not needed C-Files
*.o
*.s
*.d
# Other unwanted files
ntt_newHope.c
ntt_newHope.h
numbertheoretictransform.py
numbertheoretictransform.pyc
numbertheoretictransform-test.py
main
vscode/
work/
.xil/
.log
.jou
.gitmodules 0 → 100644
View file @ 32a70344
[submodule "picorv32"]
path = picorv32
url = https://gitlab.rhrk.uni-kl.de/epl/picorv32.git
README.md 0 → 100644
View file @ 32a70344
# Embedded Processor Lab
For further information please visit the Embedded Processor Lab Olat website.
\ No newline at end of file
modelsim/.gitignore 0 → 100644
View file @ 32a70344
*
!.gitignore
!modelsim.tcl
!wave.do
!vivado_compile
!vivado_compile.tcl
modelsim/modelsim.tcl 0 → 100644
View file @ 32a70344
# Copyright (C) 2019 Microelectronic Systems Design Research Group
# ||||
# +------+ Microelectronic Systems Design Research Group
#==| |== Department of Electrical Engineering
#==| |== University of Kaiserslautern (TUK)
# +------+ Germany
# ||||
#@file modelsim.tcl
#@author Johannes Feldmann (feldmann@eit.uni-kl.de)
#@description TCL script for automatic modelsim simulation steup
#*/
puts {
ModelSimSE premium compile script version 2.0
Microelectronic Systems Design Research Group
TU Kaiserslautern (2019)
}
# Set your rtl files here
set library_file_list {
work {
../testbenches/software_tb.sv
../rtl/sim/AXI4ROM.sv
../rtl/sim/AXI4RAM.sv
../rtl/sim/AXI4Interconnect.sv
../rtl/if/AXI4Interface.sv
../rtl/if/PCPInterface.sv
../rtl/syn/PICORV32_wrapper.sv
../rtl/syn/riscv_pcp_vhdl.vhdl
../rtl/syn/riscv_pcp_v.v
../rtl/syn/riscv_pcp_sv.sv
../picorv32/picorv32.v
}
}
# Set your top level file here
set top_level work.software_tb
# Set your wave file here
set wave wave.do
# Set your run time
set runtime 500ns
# Set your flags
set load_intel 0
set load_xilinx 1
set is_debug 0
set is_epl_sim 1
# After sourcing the script from ModelSim for the
# first time use these commands to recompile.
proc r {} {uplevel #0 source modelsim.tcl}
proc rr {} {global last_compile_time
set last_compile_time 0
r }
proc q {} {quit -force }
proc AddWave {} {
}
proc LoadIntel {} {
global env
puts "Loading Intel libraries"
if ([info exists env(QUARTUS_ROOTDIR)]) {
puts "\tQUARTUS_ROOTDIR=$env(QUARTUS_ROOTDIR)";
} else {
puts "\tPlease define QUARTUS_ROOTDIR as <Quartus installation path>";
}
vlib altera_mf_ver
vmap altera_mf_ver altera_mf_ver
vlog -reportprogress 300 -work altera_mf_ver $env(QUARTUS_ROOTDIR)/eda/sim_lib/altera_mf.v
}
proc LoadXilinx {} {
global env
puts "Loading Xilinx libraries"
if ([info exists env(XILINX_VIVADO)]) {
puts "\tVIVADO_ROOTDIR=$env(XILINX_VIVADO)";
} else {
puts "\tPlease source settings64.(c)sh";
}
if {[file exist vivado_lib]} {
puts "\tUsing cached libraries stored in vivado_lib.";
} else {
puts "\tThis might take some time. Be patient.";
exec vivado -mode tcl -source vivado_compile.tcl
puts "\tdone.";
}
}
if { [catch {open "|vsim -version" } input] } {
# If there was an error running the command,
# print it
puts $input
} else {
global env
puts "Using the following environment variables:";
if {[info exists env(MODEL_TECH)]} {
puts "\tMODEL_TECH=$env(MODEL_TECH)";
} else {
puts "Please define MODEL_TECH as <ModelSim installation path>/win32 or <ModelSim installation path>/win32aloem";
}
puts "\n";
# Prepare work library and compile design and testbench file
set last_compile_time 0
foreach {library file_list} $library_file_list {
vlib $library
foreach file $file_list {
if { $last_compile_time < [file mtime $file] } {
if [regexp {.vhdl?$} $file] {
vcom -2002 $file
} else {
if { $is_debug } {
if { $is_epl_sim } {
vlog -sv $file +define+DEBUG +define+EPL_SIM
} else {
vlog -sv $file +define+DEBUG
}
} else {
if {$is_epl_sim} {
vlog -sv $file +define+EPL_SIM
} else {
vlog -sv $file
}
}
}
set last_compile_time 0
}
}
}
if { $load_intel } {
LoadIntel
}
if { $load_xilinx } {
LoadXilinx
}
eval vsim -t ps -voptargs="+acc" $top_level -L vivado_lib/axi_crossbar_v2_1_23 -L vivado_lib/blk_mem_gen_v8_4_4 -L vivado_lib/generic_baseblocks_v2_1_0 -L vivado_lib/axi_register_slice_v2_1_22
if { [file exist $wave] } {
eval do $wave
} else {
AddWave
}
# eval run $runtime
eval run -all
}
close $input
modelsim/vivado_compile 0 → 100755
View file @ 32a70344
#!/bin/bash
vivado -mode tcl -source vivado_compile.tcl
modelsim/vivado_compile.tcl 0 → 100644
View file @ 32a70344
if { [catch {eval compile_simlib -simulator modelsim -simulator_exec_path {$env(MODEL_TECH)} -directory vivado_lib -family artix7 -language all -library all} ] } {
puts "An error occured during compile_simlib."
exit
}
exit
modelsim/wave.do 0 → 100644
View file @ 32a70344
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -expand -group ROM_AXI -color white -label clk /software_tb/axi4_rom/clk
add wave -noupdate -expand -group ROM_AXI -color white -label resetn /software_tb/axi4_rom/resetn
add wave -noupdate -expand -group ROM_AXI -group AW -color #bae096 -label awaddr /software_tb/axi4_rom/awaddr
add wave -noupdate -expand -group ROM_AXI -group AW -color #bae096 -label awvalid /software_tb/axi4_rom/awvalid
add wave -noupdate -expand -group ROM_AXI -group AW -color #fcf400 -label awready /software_tb/axi4_rom/awready
add wave -noupdate -expand -group ROM_AXI -group W -color #bae096 -label wdata /software_tb/axi4_rom/wdata
add wave -noupdate -expand -group ROM_AXI -group W -color #bae096 -label wstrb /software_tb/axi4_rom/wstrb
add wave -noupdate -expand -group ROM_AXI -group W -color #bae096 -label wlast /software_tb/axi4_rom/wlast
add wave -noupdate -expand -group ROM_AXI -group W -color #bae096 -label wvalid /software_tb/axi4_rom/wvalid
add wave -noupdate -expand -group ROM_AXI -group W -color #fcf400 -label wready /software_tb/axi4_rom/wready
add wave -noupdate -expand -group ROM_AXI -group B -color #fcf400 -label bresp /software_tb/axi4_rom/bresp
add wave -noupdate -expand -group ROM_AXI -group B -color #fcf400 -label bvalid /software_tb/axi4_rom/bvalid
add wave -noupdate -expand -group ROM_AXI -group B -color #bae096 -label bready /software_tb/axi4_rom/bready
add wave -noupdate -expand -group ROM_AXI -expand -group AR -color #bae096 -label araddr /software_tb/axi4_rom/araddr
add wave -noupdate -expand -group ROM_AXI -expand -group AR -color #bae096 -label arvalid /software_tb/axi4_rom/arvalid
add wave -noupdate -expand -group ROM_AXI -expand -group AR -color #fcf400 -label arready /software_tb/axi4_rom/arready
add wave -noupdate -expand -group ROM_AXI -expand -group R -color #fcf400 -label rdata /software_tb/axi4_rom/rdata
add wave -noupdate -expand -group ROM_AXI -expand -group R -color #fcf400 -label rresp /software_tb/axi4_rom/rresp
add wave -noupdate -expand -group ROM_AXI -expand -group R -color #fcf400 -label rlast /software_tb/axi4_rom/rlast
add wave -noupdate -expand -group ROM_AXI -expand -group R -color #bae096 -label rready /software_tb/axi4_rom/rready
add wave -noupdate -expand -group ROM_AXI -expand -group R -label rvalid /software_tb/axi4_rom/rvalid
add wave -noupdate -group CPU_AXI -color white -label clk /software_tb/intercon/s00/clk
add wave -noupdate -group CPU_AXI -color white -label resetn /software_tb/intercon/s00/resetn
add wave -noupdate -group CPU_AXI -group AW -color #fcf400 -label awaddr /software_tb/intercon/s00/awaddr
add wave -noupdate -group CPU_AXI -group AW -color #fcf400 -label awvalid /software_tb/intercon/s00/awvalid
add wave -noupdate -group CPU_AXI -group AW -color #bae096 -label awready /software_tb/intercon/s00/awready
add wave -noupdate -group CPU_AXI -group W -color #fcf400 -label wdata /software_tb/intercon/s00/wdata
add wave -noupdate -group CPU_AXI -group W -color #fcf400 -label wstrb /software_tb/intercon/s00/wstrb
add wave -noupdate -group CPU_AXI -group W -color #fcf400 -label wlast /software_tb/intercon/s00/wlast
add wave -noupdate -group CPU_AXI -group W -color #fcf400 -label wvalid /software_tb/intercon/s00/wvalid
add wave -noupdate -group CPU_AXI -group W -color #bae096 -label wready /software_tb/intercon/s00/wready
add wave -noupdate -group CPU_AXI -group B -color #bae096 -label bresp /software_tb/intercon/s00/bresp
add wave -noupdate -group CPU_AXI -group B -color #bae096 -label bvalid /software_tb/intercon/s00/bvalid
add wave -noupdate -group CPU_AXI -group B -color #fcf400 -label bready /software_tb/intercon/s00/bready
add wave -noupdate -group CPU_AXI -group AR -color #fcf400 -label araddr /software_tb/intercon/s00/araddr
add wave -noupdate -group CPU_AXI -group AR -color #fcf400 -label arvalid /software_tb/intercon/s00/arvalid
add wave -noupdate -group CPU_AXI -group AR -color #bae096 -label arready /software_tb/intercon/s00/arready
add wave -noupdate -group CPU_AXI -group R -color #bae096 -label rdata /software_tb/intercon/s00/rdata
add wave -noupdate -group CPU_AXI -group R -color #bae096 -label rresp /software_tb/intercon/s00/rresp
add wave -noupdate -group CPU_AXI -group R -color #bae096 -label rlast /software_tb/intercon/s00/rlast
add wave -noupdate -group CPU_AXI -group R -color #fcf400 -label rready /software_tb/intercon/s00/rready
add wave -noupdate -group RAM_AXI -color white -label resetn /software_tb/ram/inst/s_aresetn
add wave -noupdate -group RAM_AXI -group AW -color #bae096 -label awaddr /software_tb/ram/inst/s_axi_awaddr
add wave -noupdate -group RAM_AXI -group AW -color #bae096 -label awvalid /software_tb/ram/inst/s_axi_awvalid
add wave -noupdate -group RAM_AXI -group AW -color #fcf400 -label awready /software_tb/ram/inst/s_axi_awready
add wave -noupdate -group RAM_AXI -group W -color #bae096 -label wdata /software_tb/ram/inst/s_axi_wdata
add wave -noupdate -group RAM_AXI -group W -color #bae096 -label wlast /software_tb/ram/inst/s_axi_wlast
add wave -noupdate -group RAM_AXI -group W -color #bae096 -label wvalid /software_tb/ram/inst/s_axi_wvalid
add wave -noupdate -group RAM_AXI -group W -color #fcf400 -label wready /software_tb/ram/inst/s_axi_wready
add wave -noupdate -group RAM_AXI -group B -color #fcf400 -label bresp /software_tb/ram/inst/s_axi_bresp
add wave -noupdate -group RAM_AXI -group B -color #fcf400 -label bvalid /software_tb/ram/inst/s_axi_bvalid
add wave -noupdate -group RAM_AXI -group B -color #bae096 -label bready /software_tb/ram/inst/s_axi_bready
add wave -noupdate -group RAM_AXI -group AR -color #bae096 -label araddr /software_tb/ram/inst/s_axi_araddr
add wave -noupdate -group RAM_AXI -group AR -color #bae096 -label arvalid /software_tb/ram/inst/s_axi_arvalid
add wave -noupdate -group RAM_AXI -group AR -color #fcf400 -label arready /software_tb/ram/inst/s_axi_arready
add wave -noupdate -group RAM_AXI -group R -color #fcf400 -label rdata /software_tb/ram/inst/s_axi_rdata
add wave -noupdate -group RAM_AXI -group R -color #fcf400 -label rresp /software_tb/ram/inst/s_axi_rresp
add wave -noupdate -group RAM_AXI -group R -color #fcf400 -label rlast /software_tb/ram/inst/s_axi_rlast
add wave -noupdate -group RAM_AXI -group R -color #bae096 -label rready /software_tb/ram/inst/s_axi_rready
add wave -noupdate -expand -group CPU -label programcounter /software_tb/cpu/cpu/picorv32_core/reg_pc
add wave -noupdate -expand -group CPU -clampanalog 1 -format Analog-Step -label stackpointer -max 268440000.0 -min 268435000.0 {/software_tb/cpu/cpu/picorv32_core/cpuregs[2]}
add wave -noupdate -expand -group CPU -label cpuregs /software_tb/cpu/cpu/picorv32_core/cpuregs
add wave -noupdate -expand -group CPU -label trap /software_tb/cpu/cpu/picorv32_core/trap
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {195010 ps} 0} {{Cursor 2} {19220631166 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 161
configure wave -valuecolwidth 114
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {689960 ps}
picorv32/.gitignore 0 → 100644
View file @ 32a70344
/tests/*.o
/firmware/*.o
/firmware/firmware.bin
/firmware/firmware.elf
/firmware/firmware.hex
/firmware/firmware.map
/dhrystone/dhry.bin
/dhrystone/dhry.elf
/dhrystone/dhry.hex
/dhrystone/dhry.map
/dhrystone/testbench.vvp
/dhrystone/testbench.vcd
/dhrystone/testbench_nola.vvp
/dhrystone/testbench_nola.vcd
/dhrystone/timing.vvp
/dhrystone/timing.txt
/dhrystone/*.d
/dhrystone/*.o
/riscv-gnu-toolchain-riscv32i
/riscv-gnu-toolchain-riscv32ic
/riscv-gnu-toolchain-riscv32im
/riscv-gnu-toolchain-riscv32imc
/testbench.vvp
/testbench_wb.vvp
/testbench_ez.vvp
/testbench_sp.vvp
/testbench_rvf.vvp
/testbench_synth.vvp
/testbench.gtkw
/testbench.vcd
/testbench.trace
/testbench_verilator*
/check.smt2
/check.vcd
/synth.log
/synth.v
.*.swp
picorv32/Makefile 0 → 100644
View file @ 32a70344
RISCV_GNU_TOOLCHAIN_GIT_REVISION = 411d134
RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX = /opt/riscv32
# Give the user some easy overrides for local configuration quirks.
# If you change one of these and it breaks, then you get to keep both pieces.
SHELL = bash
PYTHON = python3
VERILATOR = verilator
ICARUS_SUFFIX =
IVERILOG = iverilog$(ICARUS_SUFFIX)
VVP = vvp$(ICARUS_SUFFIX)
TEST_OBJS = $(addsuffix .o,$(basename $(wildcard tests/*.S)))
FIRMWARE_OBJS = firmware/start.o firmware/irq.o firmware/print.o firmware/hello.o firmware/sieve.o firmware/multest.o firmware/stats.o
GCC_WARNS = -Werror -Wall -Wextra -Wshadow -Wundef -Wpointer-arith -Wcast-qual -Wcast-align -Wwrite-strings
GCC_WARNS += -Wredundant-decls -Wstrict-prototypes -Wmissing-prototypes -pedantic # -Wconversion
TOOLCHAIN_PREFIX = $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i/bin/riscv32-unknown-elf-
COMPRESSED_ISA = C
# Add things like "export http_proxy=... https_proxy=..." here
GIT_ENV = true
test: testbench.vvp firmware/firmware.hex
$(VVP) -N $<
test_vcd: testbench.vvp firmware/firmware.hex
$(VVP) -N $< +vcd +trace +noerror
test_rvf: testbench_rvf.vvp firmware/firmware.hex
$(VVP) -N $< +vcd +trace +noerror
test_wb: testbench_wb.vvp firmware/firmware.hex
$(VVP) -N $<
test_wb_vcd: testbench_wb.vvp firmware/firmware.hex
$(VVP) -N $< +vcd +trace +noerror
test_ez: testbench_ez.vvp
$(VVP) -N $<
test_ez_vcd: testbench_ez.vvp
$(VVP) -N $< +vcd
test_sp: testbench_sp.vvp firmware/firmware.hex
$(VVP) -N $<
test_axi: testbench.vvp firmware/firmware.hex
$(VVP) -N $< +axi_test
test_synth: testbench_synth.vvp firmware/firmware.hex
$(VVP) -N $<
test_verilator: testbench_verilator firmware/firmware.hex
./testbench_verilator
testbench.vvp: testbench.v picorv32.v
$(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
chmod -x $@
testbench_rvf.vvp: testbench.v picorv32.v rvfimon.v
$(IVERILOG) -o $@ -D RISCV_FORMAL $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
chmod -x $@
testbench_wb.vvp: testbench_wb.v picorv32.v
$(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
chmod -x $@
testbench_ez.vvp: testbench_ez.v picorv32.v
$(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) $^
chmod -x $@
testbench_sp.vvp: testbench.v picorv32.v
$(IVERILOG) -o $@ $(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) -DSP_TEST $^
chmod -x $@
testbench_synth.vvp: testbench.v synth.v
$(IVERILOG) -o $@ -DSYNTH_TEST $^
chmod -x $@
testbench_verilator: testbench.v picorv32.v testbench.cc
$(VERILATOR) --cc --exe -Wno-lint -trace --top-module picorv32_wrapper testbench.v picorv32.v testbench.cc \
$(subst C,-DCOMPRESSED_ISA,$(COMPRESSED_ISA)) --Mdir testbench_verilator_dir
$(MAKE) -C testbench_verilator_dir -f Vpicorv32_wrapper.mk
cp testbench_verilator_dir/Vpicorv32_wrapper testbench_verilator
check: check-yices
check-%: check.smt2
yosys-smtbmc -s $(subst check-,,$@) -t 30 --dump-vcd check.vcd check.smt2
yosys-smtbmc -s $(subst check-,,$@) -t 25 --dump-vcd check.vcd -i check.smt2
check.smt2: picorv32.v
yosys -v2 -p 'read_verilog -formal picorv32.v' \
-p 'prep -top picorv32 -nordff' \
-p 'assertpmux -noinit; opt -fast' \
-p 'write_smt2 -wires check.smt2'
synth.v: picorv32.v scripts/yosys/synth_sim.ys
yosys -qv3 -l synth.log scripts/yosys/synth_sim.ys
firmware/firmware.hex: firmware/firmware.bin firmware/makehex.py
$(PYTHON) firmware/makehex.py $< 32768 > $@
firmware/firmware.bin: firmware/firmware.elf
$(TOOLCHAIN_PREFIX)objcopy -O binary $< $@
chmod -x $@
firmware/firmware.elf: $(FIRMWARE_OBJS) $(TEST_OBJS) firmware/sections.lds
$(TOOLCHAIN_PREFIX)gcc -Os -ffreestanding -nostdlib -o $@ \
-Wl,-Bstatic,-T,firmware/sections.lds,-Map,firmware/firmware.map,--strip-debug \
$(FIRMWARE_OBJS) $(TEST_OBJS) -lgcc
chmod -x $@
firmware/start.o: firmware/start.S
$(TOOLCHAIN_PREFIX)gcc -c -march=rv32im$(subst C,c,$(COMPRESSED_ISA)) -o $@ $<
firmware/%.o: firmware/%.c
$(TOOLCHAIN_PREFIX)gcc -c -march=rv32i$(subst C,c,$(COMPRESSED_ISA)) -Os --std=c99 $(GCC_WARNS) -ffreestanding -nostdlib -o $@ $<
tests/%.o: tests/%.S tests/riscv_test.h tests/test_macros.h
$(TOOLCHAIN_PREFIX)gcc -c -march=rv32im -o $@ -DTEST_FUNC_NAME=$(notdir $(basename $<)) \
-DTEST_FUNC_TXT='"$(notdir $(basename $<))"' -DTEST_FUNC_RET=$(notdir $(basename $<))_ret $<
download-tools:
sudo bash -c 'set -ex; mkdir -p /var/cache/distfiles; $(GIT_ENV); \
$(foreach REPO,riscv-gnu-toolchain riscv-binutils-gdb riscv-gcc riscv-glibc riscv-newlib, \
if ! test -d /var/cache/distfiles/$(REPO).git; then rm -rf /var/cache/distfiles/$(REPO).git.part; \
git clone --bare https://github.com/riscv/$(REPO) /var/cache/distfiles/$(REPO).git.part; \
mv /var/cache/distfiles/$(REPO).git.part /var/cache/distfiles/$(REPO).git; else \
(cd /var/cache/distfiles/$(REPO).git; git fetch https://github.com/riscv/$(REPO)); fi;)'
define build_tools_template
build-$(1)-tools:
@read -p "This will remove all existing data from $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)). Type YES to continue: " reply && [[ "$$$$reply" == [Yy][Ee][Ss] || "$$$$reply" == [Yy] ]]
sudo bash -c "set -ex; rm -rf $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); mkdir -p $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); chown $$$${USER}: $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1))"
+$(MAKE) build-$(1)-tools-bh
build-$(1)-tools-bh:
+set -ex; $(GIT_ENV); \
if [ -d /var/cache/distfiles/riscv-gnu-toolchain.git ]; then reference_riscv_gnu_toolchain="--reference /var/cache/distfiles/riscv-gnu-toolchain.git"; else reference_riscv_gnu_toolchain=""; fi; \
if [ -d /var/cache/distfiles/riscv-binutils-gdb.git ]; then reference_riscv_binutils_gdb="--reference /var/cache/distfiles/riscv-binutils-gdb.git"; else reference_riscv_binutils_gdb=""; fi; \
if [ -d /var/cache/distfiles/riscv-gcc.git ]; then reference_riscv_gcc="--reference /var/cache/distfiles/riscv-gcc.git"; else reference_riscv_gcc=""; fi; \
if [ -d /var/cache/distfiles/riscv-glibc.git ]; then reference_riscv_glibc="--reference /var/cache/distfiles/riscv-glibc.git"; else reference_riscv_glibc=""; fi; \
if [ -d /var/cache/distfiles/riscv-newlib.git ]; then reference_riscv_newlib="--reference /var/cache/distfiles/riscv-newlib.git"; else reference_riscv_newlib=""; fi; \
rm -rf riscv-gnu-toolchain-$(1); git clone $$$$reference_riscv_gnu_toolchain https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain-$(1); \
cd riscv-gnu-toolchain-$(1); git checkout $(RISCV_GNU_TOOLCHAIN_GIT_REVISION); \
git submodule update --init $$$$reference_riscv_binutils_gdb riscv-binutils; \
git submodule update --init $$$$reference_riscv_binutils_gdb riscv-gdb; \
git submodule update --init $$$$reference_riscv_gcc riscv-gcc; \
git submodule update --init $$$$reference_riscv_glibc riscv-glibc; \
git submodule update --init $$$$reference_riscv_newlib riscv-newlib; \
mkdir build; cd build; ../configure --with-arch=$(2) --prefix=$(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)$(subst riscv32,,$(1)); make
.PHONY: build-$(1)-tools
endef
$(eval $(call build_tools_template,riscv32i,rv32i))
$(eval $(call build_tools_template,riscv32ic,rv32ic))
$(eval $(call build_tools_template,riscv32im,rv32im))
$(eval $(call build_tools_template,riscv32imc,rv32imc))
build-tools:
@echo "This will remove all existing data from $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)i, $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)ic, $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)im, and $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX)imc."
@read -p "Type YES to continue: " reply && [[ "$$reply" == [Yy][Ee][Ss] || "$$reply" == [Yy] ]]
sudo bash -c "set -ex; rm -rf $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}; mkdir -p $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}; chown $${USER}: $(RISCV_GNU_TOOLCHAIN_INSTALL_PREFIX){i,ic,im,imc}"
+$(MAKE) build-riscv32i-tools-bh
+$(MAKE) build-riscv32ic-tools-bh
+$(MAKE) build-riscv32im-tools-bh
+$(MAKE) build-riscv32imc-tools-bh
toc:
gawk '/^-+$$/ { y=tolower(x); gsub("[^a-z0-9]+", "-", y); gsub("-$$", "", y); printf("- [%s](#%s)\n", x, y); } { x=$$0; }' README.md
clean:
rm -rf riscv-gnu-toolchain-riscv32i riscv-gnu-toolchain-riscv32ic \
riscv-gnu-toolchain-riscv32im riscv-gnu-toolchain-riscv32imc
rm -vrf $(FIRMWARE_OBJS) $(TEST_OBJS) check.smt2 check.vcd synth.v synth.log \
firmware/firmware.elf firmware/firmware.bin firmware/firmware.hex firmware/firmware.map \
testbench.vvp testbench_sp.vvp testbench_synth.vvp testbench_ez.vvp \
testbench_rvf.vvp testbench_wb.vvp testbench.vcd testbench.trace \
testbench_verilator testbench_verilator_dir
.PHONY: test test_vcd test_sp test_axi test_wb test_wb_vcd test_ez test_ez_vcd test_synth download-tools build-tools toc clean
picorv32/README.md 0 → 100644
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picorv32/dhrystone/Makefile 0 → 100644
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USE_MYSTDLIB = 0
OBJS = dhry_1.o dhry_2.o stdlib.o
CFLAGS = -MD -O3 -march=rv32im -DTIME -DRISCV
TOOLCHAIN_PREFIX = /opt/riscv32im/bin/riscv32-unknown-elf-
ifeq ($(USE_MYSTDLIB),1)
CFLAGS += -DUSE_MYSTDLIB -ffreestanding -nostdlib
OBJS += start.o
else
OBJS += syscalls.o
endif
test: testbench.vvp dhry.hex
vvp -N testbench.vvp
test_trace: testbench.vvp dhry.hex
vvp -N $< +trace
python3 ../showtrace.py testbench.trace dhry.elf > testbench.ins
test_nola: testbench_nola.vvp dhry.hex
vvp -N testbench_nola.vvp
timing: timing.txt
grep '^##' timing.txt | gawk 'x != "" {print x,$$3-y;} {x=$$2;y=$$3;}' | sort | uniq -c | \
gawk '{printf("%03d-%-7s %2d %-8s (%d)\n",$$3,$$2,$$3,$$2,$$1);}' | sort | cut -c13-
timing.txt: timing.vvp dhry.hex
vvp -N timing.vvp > timing.txt
testbench.vvp: testbench.v ../picorv32.v
iverilog -o testbench.vvp testbench.v ../picorv32.v
chmod -x testbench.vvp
testbench_nola.vvp: testbench_nola.v ../picorv32.v
iverilog -o testbench_nola.vvp testbench_nola.v ../picorv32.v
chmod -x testbench_nola.vvp
timing.vvp: testbench.v ../picorv32.v
iverilog -o timing.vvp -DTIMING testbench.v ../picorv32.v
chmod -x timing.vvp
dhry.hex: dhry.elf
$(TOOLCHAIN_PREFIX)objcopy -O verilog $< $@
ifeq ($(USE_MYSTDLIB),1)
dhry.elf: $(OBJS) sections.lds
$(TOOLCHAIN_PREFIX)gcc $(CFLAGS) -Wl,-Bstatic,-T,sections.lds,-Map,dhry.map,--strip-debug -o $@ $(OBJS) -lgcc
chmod -x $@
else
dhry.elf: $(OBJS)
$(TOOLCHAIN_PREFIX)gcc $(CFLAGS) -Wl,-Bstatic,-T,../firmware/riscv.ld,-Map,dhry.map,--strip-debug -o $@ $(OBJS) -lgcc -lc
chmod -x $@
endif
%.o: %.c
$(TOOLCHAIN_PREFIX)gcc -c $(CFLAGS) $<
%.o: %.S
$(TOOLCHAIN_PREFIX)gcc -c $(CFLAGS) $<
dhry_1.o dhry_2.o: CFLAGS += -Wno-implicit-int -Wno-implicit-function-declaration
clean:
rm -rf *.o *.d dhry.elf dhry.map dhry.bin dhry.hex testbench.vvp testbench.vcd timing.vvp timing.txt testbench_nola.vvp
.PHONY: test clean
-include *.d
picorv32/dhrystone/README 0 → 100644
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The Dhrystone benchmark and a verilog testbench to run it.
picorv32/dhrystone/dhry.h 0 → 100644
View file @ 32a70344
/*
****************************************************************************
*